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ModelSim Advanced Debugging - Student Workbook 5.6
- 这是mentor公司modelsim软件的高级调试技巧培训。对于从事可编程逻辑系统开发的工程师们,这是非常必要掌握的知识。-modelsim software company's senior debugging skills training. Having engaged in the development of programmable logic system engineers, it is necessary to grasp knowledge.
ModelSim_SE_6.1bkey
- ModelSim SE 6.1 (电子仿真)具体破解-ModelSim SE 6.1 (electronic simulation) Specific crack
SPI_verilogHDL
- 本原码是基于Verilog HDL语言编写的,实现了SPI接口设计,可以应用于FPGA,实现SPI协议的接口设计.在MAXII编译成功,用Modelsim SE 6仿真成功.-primitive code is based on Verilog HDL language, and achieving the SPI interface design, FPGA can be used to achieve agreement SPI interface design. MAXII success
Fir
- 11 阶FIR 数字滤波器,verolog描述,通过modelsim 6.0 仿真,Quartue综合
FIFO_Syn
- 同步FIFO功能,verilog语言描述,通过了modelsim 6.0 仿真,Quartue综合
4VerilogFIFO
- 一种新的FIFO实现方法,verilog描述,通过modelsim 6.0 仿真,Quartue综合
circularbuffer
- Circular_Buffer,流水线型多位缓存器,verilog语言描述。通过modelsim 6。0仿真,quartus 综合通过。
4_in_1
- 骏龙提供的最新quartus8.0的license,包括Quartus II 8.0,NIOS II 8.0(在Quartus II的license里面),DSP Builde 8.0,ModelSim-Altera 6.1g (Quartus II 8.0),新Quartus II的license支持远程桌面访问的功能。
sell
- 软件开发环境:ISE 7.1i 仿真环境:ModelSim SE 6.0 1. 自动售饮机 电话计费器程序-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Drink vending machine telephone billing program
yuelao
- 软件开发环境:ISE 7.1i 仿真环境:ModelSim SE 6.0 1. 用VHDL语言仿真歌曲刘德华的《月老》-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Using VHDL simulation language song Andy Lau' s " 月老"
ModelSim_SE_6.5_downloads_install_Configuration.ra
- 详细的介绍了modelsim的下载,破解,编译xilinx库,配置的问题,非常详细-Described in detail modelsim download, crack, the compiler library xilinx, configuration problems, in great detail
Crack_patch
- Modelsim se 6.1b 破解程序 ,但是没有LICENSE.DAT文件-Modelsim se 6.1b crack program, but did not LICENSE.DAT file
Altera_FPGA_develop(QuartusII_7.2_ModelSim_6.5).ra
- Altera FPGA开发说明(QuartusII 7.2 & ModelSim 6.5).pdf 建立和编译QII项目 modelsim功能仿真 QII引脚分配 modelsim时序仿真(建立Altera仿真库) QII下载 -Altera FPGA Development Descr iption (QuartusII 7.2 & ModelSim 6.5). Pdf project to establish and build QII QII pin ass
NET2
- This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, usi
modelsimPcrack
- modelsim 的crack,能够破解6.5se-modelsim of the crack, to break 6.5se
modelsim-SE-6.5keygen
- use, u can automatically delete the directory -use, u can automatically delete the directory
modelsim-6.0
- 硬件描述语言仿真工具modelsim 6.0的附图详细教程-the detail tutorial of modelsim 6.0 with pictures
modelsim-SE-PLUS-6.5
- 自己总结的关于modelsim6.5的一些用法,希望可以与大家分享-something on the use of modelsim 6.5
ex1
- 设计一个循环灯控制器,该控制器控制红、绿、黄三个发光管循环发亮。要求红发光管亮2秒,绿发光管亮3秒,黄发光管亮1秒。(假设外部提供频率为1MHz的方波信号) 编程环境为Quartus II 11.0 仿真环境为 Modelsim 6.6d 通过仿真可以看出。系统复位后,红发光管亮2秒,绿发光管亮3秒,黄发光管亮1秒,三个发光管循环发亮。 -Design a loop lamp controller that controls the red, green and ye
ModelSim-
- 此资料为modelsim使用教程6.0,包括初学者全套中文资料,为初学者提供很大帮组。-This information is modelsim tutorial 6.0, including a full set of Chinese information for beginners, providing great help group for the beginner.